Tri State Buffer | Three State Buffer

Tri State Buffer

A common bus system can be implemented using tri-state or three-state gates instead of multiplexers. A tri-state gate is a digital circuit that can have three output states High, Low and High Impedance. The high impedance state behaves like an open circuit, which mean that the output is disconnected.

We know that bus is common connection between number of registers and other units. The data transfer through tri-state gates may require larger sinking and sourcing of current. The tri-state gate which provides more sinking and sourcing capacities is called tri-state buffer.

 

Figure : Tri State Buffer

Connection of Tri State Buffer with Register

How the data transfer takes place between register and common bus. Here, 4-bit register is shown with tri-state buffer at input and output sides. Each data line requires two tri-state buffers one at the input side and one at the output side. In diagram, all tri-state buffers at the input side are control by a common control signal R_in, and output side are control by a common control signal R_out.

 

Figure : Connection of Tri state buffer with register

Common Bus Structure (Using Tri State buffer)

Figure shows the bus structure for the data transfer between various register and the common bus. As shown in figure each register has input and output tri state buffers and these tri state buffers are controlled by corresponding control signals. Control signals R_i in is set to 1, the data available on the common data bus is loaded into register R_i. Similarly, when Ri out is set to 1, the contents of register R_i are placed on the common data bus. The signals R_i in and R_i out are commonly known as input enable and output enable signals of registers, respectively.

Figure : Common bus structure using tri state buffer

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