Chirag's Blog: Tightly Coupled Multiprocessors

Introduction

Multiprocessors are classified by the way their memory is organized.

Multiprocessor system with common shared memory is classified as a shared memory or tightly coupled multiprocessor.

Tightly Coupled Multiprocessors

In this system the processors share clock generator, bus control logic, entire memory and I/O system. These systems communicate through a memory. One of the limitations of this system is the performance degradation due to memory contentions which occur when two or more processors attempt the same memory unit simultaneously. When high speed of real-time processing is desired, this system may be used.

Tightly Coupled Multiprocessors (Without Private Cache)

This system consists of following things: P processors, M memory modules, C input-output channels.

Figure : Tightly Coupled Multiprocessors without private cache

These units are connected through a set of three interconnected networks.

PMIN: processor-memory interconnection network

IOPIN: input-output processor interconnection network

ISIN: interrupt-signal interconnection network

The PMIN is a switch which is used to connect every processor to every memory module. The IOPIN is used to allow a processor to communicate with an I/O channel which is connected to I/O devices. The ISIN is used for two purposes: To direct an interrupt to any other inter-processor network and to initiate hardware alarm in case of processor failure. There is no separate private cache memory to any processor.

Tightly Coupled Multiprocessors (With Private Cache)

In previous method each memory reference goes through the PMIN, it encounters delay in the processor or memory switch and hence the instruction cycle time is increases. It reduces system throughput. This delay can be reduced by associating a cache with each processor. Another advantage of the cache is that the traffic through the crossbar switch can be reduced. More than one inconsistent copy of data may exist in the system as this multiprocessor system encounter cache coherence problem.