Parallel Arbitration in multiprocessor

 

Inter Processor Arbitration

The processor, main memory and I/O devices can be interconnected by means of a common bus. A bus is set of lines (wires) defined to transfer all bits of a word from a specified source to a specified destination. Thus, bus provides a communication path for the transfer of data.

The bus includes data lines, address lines and control lines. Such a bus known as system bus. Different types of arbitration: Serial (Daisy Chain) arbitration, Parallel arbitration, Dynamic arbitration.

Parallel Arbitration

In this technique uses an external priority encoder and decoder as shown in figure below. Each bus arbiter in the parallel scheme has a bus request output line and a bus acknowledge input line. When processor wants to access system bus at that time arbiter of that processor enables request line. The processor takes control of the bus if it acknowledges input line is enabled.

 

Figure : Parallel Arbitration

Figure shows the request lines from four arbiters going into a 4 x 2 priority encoder. The output of the encoder generates a 2-bit code, which represents the highest-priority unit among those requesting the bus. The 2-bit code from the encoder output drives a 2×4 decoder which enables the proper acknowledge line to grant bus access to the highest-priority unit. It works on priority encoder truth table.

Advantage

Separate pair of bus request and bus grant signals, so it is faster.

Disadvantage

Require more bus request and grant signal.

To learn more about Parallel Arbitration, watch below video

Video : Parallel Arbitration

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