Multiport memory in Multiprocessor System

 

Different schemes of interconnection structure are:

Multiport Memory

A multiport memory system employs separate buses between each memory module and each CPU. As shown in figure below for four CPUs and four memory modules (MMs).

 

Figure : Multiprot Memory

Each processor bus is connected to each memory module. A processor bus consists of the address, data, and control lines required to communicate with memory. The memory module is said to have four ports and each port accommodates one of the buses. The module must have internal control logic to determine which port will have access to memory at any given time. Memory access conflicts are resolved by assigning fixed priorities to each memory port. The priority for memory access based on physical port position. Thus, CPU1 will have priority over CPU2, CPU2 will have priority over CPU3, and CPU4 will have the lowest priority. This interconnection structure is usually appropriate for systems with a small number of processors.

Advantage

Higher transfer rate achieved due to multiple paths between processors and memory.

Disadvantages

Require expensive memory control logic

Require large number of cables and connectors

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Video : Multiport Memory

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