Inter Processor Arbitration
The
processor, main memory and I/O devices can be interconnected by means of a
common bus. A bus is set of lines (wires) defined to transfer all bits of a
word from a specified source to a specified destination. Thus, bus provides a
communication path for the transfer of data.
The bus
includes data lines, address lines and control lines. Such a bus known as system
bus. Different types of arbitration: Serial (Daisy Chain) arbitration, Parallel
arbitration, Dynamic arbitration.
Dynamic Arbitration
Discussed
two bus arbitration procedures use a static priority algorithm. The priority of
each device is fixed by the way it is connected to the bus. In contrast, a
dynamic priority algorithm gives the system the capability for changing the
priority of the devices while the system is in operation. Few dynamic
arbitration procedures that use dynamic priority algorithms: Time Slice, Polling,
LRU, FIFO
Time
Slice: In this algorithm allocates a fixed-length time slice of bus
time that is offered to each processor in sequentially manner, in round-robin
fashion. The service provide to each processor with this scheme is independent
of its location along the bus. No preference is given to any particular device
since each is allotted the same amount of time to communicate with the bus.
Polling: In a bus
system that uses polling, the bus-grant signal is replaced by a set of lines
called poll lines, which are connected to all units. Poll lines are used by the
bus controller to define an address for each device connected to the bus. The
bus controller, arrange address in a sequence through prescribed manner. When a
processor that recognizes its address, it activates the bus busy-line and then
accesses the bus. After a number of bus cycles, the polling process continues
by choosing a different processor. The polling sequence is normally
programmable, and as a result, the selection priority can be randomly under
program control.
LRU: The LRU
(least recently used) algorithm gives the highest priority to the requesting
device that has not used the bus for the longest interval. The priorities are
adjusted after a number of bus cycles according to the LRU algorithm. With this
procedure, no processor is favoured over any other since the priorities are
dynamically changed to give every device an opportunity to access the bus.
FIFO: In the
first-come, first-serve scheme, requests are served in the order received. To implement
this algorithm, the bus controller establishes a queue arranged according to
the time that the bus requests arrive. Each processor must wait for its turn to
use the bus on a first-in, first-out (FIFO) basis.
Advantages
The
priority can be changed by altering the sequence stored in controller.
More
reliable.
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