Time Shared Common Bus in multiprocessor system

 

Different schemes of interconnection structure are:

Time Shared Common Bus

A common-bus multiprocessor system consists of a number of processors connected through a common path to a memory unit. (As shown in figure) Only one processor can communicate with the memory or another processor at any given time. Transfer operations are conducted by the processor that is in control of the bus at the time.

 

Figure : Shared Memory Unit

Any other processor wants to transfer, first check the availability of the bus. When bus is available, processor address the destination unit to initiate the transfer. A command is issued to inform the destination unit what operation is to be performed. The receiving unit recognizes its address in the bus and responds to the control signals from the sender, after which the transfer is initiated. The system may exhibit transfer conflicts since one common bus is shared by all processors. These conflicts must be resolved by incorporating a bus controller that establishes priorities among the requesting units. A single common-bus system is restricted to one transfer at a time. This means that when one processor is communicating with the memory, all other processors are either busy with internal operations or must be idle waiting for the bus. As a consequence, the total overall transfer rate within the system is limited due to single path communication. Performance of the system can increase, if two or more independent buses to permit simultaneous bus transfer. However, this increases the system cost and complexity.

 

Figure : Time Shared Common Bus

A more economical implementation of a dual bus structure is shown in figure. Here we have a number of local buses each connected to its own local memory and to one or more processors. Each local bus may be connected to a CPU, an IOP, or any combination of processors. A system bus controller links each local bus to a common system bus. The I/O devices connected to the local IOP, as well as the local memory, are available to the local processor. The common shared memory connected to the common system-bus is shared by all processors. If an IOP can connected directly to the system bus, the I/O devices attached to it may be made available to all processors. Only one processor can communicate with the shared memory through system bus.

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